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? semiconductor components industries, llc, 2008 september, 2008 ? rev. 19 1 publication order number: cs8101/d cs8101 micropower 5.0 v, 100 ma low dropout linear regulator with reset and enable the cs8101 is a precision 5.0 v micropower voltage regulator with very low quiescent current (70 a typ at 100 a load). the 5.0 v output is accurate within 2.0% and supplies 100 ma of load current with a typical dropout voltage of only 400 mv. microprocessor control logic includes an enable input and an active reset . this combination of low quiescent current, outstanding regulator performance and control logic makes the cs8101 ideal for any battery operated, microprocessor controlled equipment. the active reset circuit includes hyst eresis, and operates correctly at an output voltage as low as 1.0 v. the reset function is activated during the power up sequence or during normal operation if the output voltage drops outside th e regulation limits by more than 200 mv typ. the logic level compatible enable input allows the user to put the regulator into a shutdow n mode where it draws only 20 a typical of quiescent current. the regulator is protected against reverse battery, short circuit, over voltage, and thermal overload conditions. the device can withstand load dump transients making it suitable for use in automotive environments. the cs8101 is functionally e quivalent to the national semiconductor lp2951 series low current regulators. features ? 5.0 v 2.0% output ? low 70 a quiescent current ? active reset ? enable input for on/off and active/sleep mode control ? 100 ma output current capability ? fault protection ? +60 v peak transient voltage ? ? 15 v reverse voltage short circuit thermal overload ? low reverse current (output to input) ? internally fused leads available in so ? 20 wb package ? these are pb ? free devices see detailed ordering and shipping information in the package dimensions sect ion on page 9 of this data sheet. ordering information see general marking information in the device marking section on page 9 of this data sheet. device marking information so ? 20 wb dwf suffix case 751d 1 20 soic ? 8 d suffix case 751 1 8 http://onsemi.com
cs8101 http://onsemi.com 2 pin connections reset gnd 18 nc enable nc v out sense v in v out 1 20 nc nc gnd gnd gnd gnd gnd gnd gnd gnd nc nc v in nc v out enable nc nc nc reset so ? 20wb soic ? 8 enable + ? bandgap reference ? + sense current limit gnd reset v out sense v out error amplifier figure 1. block diagram v in current source (circuit bias) over voltage shutdown thermal protection reset com- parator internally connected on so ? 20wb
cs8101 http://onsemi.com 3 maximum ratings* rating value unit power dissipation internally limited ? peak transient voltage (46 v load dump @ v in = 14 v) ? 15, 60 v operating dc voltage 30 v enable (up to v in with external resistor) 10 v output current internally limited ? esd susceptibility (human body model) 2.0 kv esd susceptibility (machine model) 200 v operating temperature ? 40 to +125 c junction temperature range ? 40 to +150 c storage temperature range ? 55 to +150 c lead temperature soldering: wave solder (through hole styles only) (note 1) reflow (smd styles only) (notes 2 & 3) 260 peak 240 peak c c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 1. 10 second maximum. 2. 60 second maximum above 183 c. 3. ? 5 c / +0 c allowable conditions. *the maximum package power dissipation must be observed. electrical characteristics (6.0 v v in 26 v; i out = 1.0 ma; ? 40 t a 125, ? 40 c t j 150 c, unless otherwise noted.) characteristic test conditions min typ max unit output stage output voltage, v out 9.0 v < v in < 16 v, 100 a i out 100 ma 6.0 v < v in < 26 v, 100 a i out 100 ma 4.90 4.85 5.00 5.00 5.10 5.15 v v dropout voltage (v in ? v out ) i out = 100 ma i out = 100 a ? ? 400 100 600 150 mv mv load regulation v in = 14 v, 100 a i out 100 ma ? 5.0 50 mv line regulation 6.0 < v < 26 v, i out = 1.0 ma ? 5.0 50 mv quiescent current, (i q ) active mode i out = 100 a, v in = 6.0 v i out = 50 ma i out = 100 ma ? ? ? 70 4.0 12 140 6.0 20 a ma ma quiescent current, (i q ) sleep mode v out = off, v in = 6.0 v, v enable = 2.0 v ? 20 50 a ripple rejection 7.0 v in 17 v, i out = 100 ma, f = 120 hz 60 75 ? db current limit ? 105 200 ? ma short circuit output current v out = 0 v 25 125 ? ma thermal shutdown ? 150 180 ? c overvoltage shutdown v out 1.0 v 30 34 38 v reverse current v out = 5.0 v, v in = 0 v ? 100 200 a
cs8101 http://onsemi.com 4 electrical characteristics (continued) (6.0 v v in 26 v; i out = 1.0 ma; ? 40 t a 125, ? 40 c t j 150 c, unless otherwise noted.) characteristic unit max typ min test conditions enable input (enable ) threshold high low (v out off) (v out on) ? 0.6 1.4 1.4 2.0 ? v v input current v enable = 2.4 v ? 30 100 a reset functions (reset ) reset threshold high (v rh ) low (v rl ) v out increasing v out decreasing 4.525 4.500 4.75 4.70 v out ? 0.05 v out ? 0.075 v v reset hysteresis (high ? low) 25 50 100 mv reset output leakage reset = high v out v rh ? ? 25 a output voltage low (v rlo ) low (vr peak ) 1.0 v v out v rl, r reset = 10 k v out , power up, power down, r reset = 10 k ? ? 0.1 0.6 0.4 1.0 v v package lead description package lead # so ? 20 wb soic ? 8 lead symbol function 20 1 v out 5.0 v, 2.0%, 100 ma output. ? 2 v out sense kelvin connection which allows remote sensing of output voltage for improved regulation. if remote sensing is not required, connect to v out . 1 3 enable logic level switches output off when toggled high. 4, 5, 6, 7 14, 15, 16, 17 4 gnd ground. all gnd leads must be connected to ground. 10 5 reset active reset (accurate to v out 1.0 v) 2, 3, 8, 9, 11, 12, 13, 18 6,7 nc no connection. true no ? connect (i.e. is floating) 19 8 v in input voltage.
cs8101 http://onsemi.com 5 typical performance characteristics load (ma) 0 1020304050607080 figure 2. cs8101 dropout voltage vs. load over temperature 0.6 0.5 0.4 0.3 0.2 0.1 0 dropout voltage 25 c 90 100 125 c ? 40 c circuit description voltage reference and output circuitry output stage protection the output stage is protected against overvoltage, short circuit and thermal runaway conditions (figure 3). figure 3. typical circuit waveforms for output stage protection i out load dump v in v out current limit short circuit > 30 v if the input voltage rises above 30 v (e.g. load dump), the output shuts down. this response protects the internal circuitry and enables the ic to survive unexpected voltage transients. should the junction temperature of the power device exceed 180 c (typ) the load current capability is reduced thereby preventing thermal overload. this thermal management function is an effective means to prevent die overheating since the load current is the principle heat source in the ic. regulator control functions the cs8101 contains two microprocessor compatible control functions: enable and reset (figure 4). figure 4. circuit waveform (1) = no reset delay capacitor v in v out enable reset (2) = with reset delay capacitor vr lo vr peak vr peak for 7.0 v < v in < 26 v v in(h) v rh v rl (1) (2) enable function the enable function switches the output transistor on and off. when the voltage on the enable lead exceeds 1.4 v typ, the output pass transistor turns off, leaving a high impedance facing the load. the ic will remain in sleep mode, drawing only 50 a, until the voltage on this input drops below the enable threshold. reset function a reset signal (low voltage) is generated as the ic powers up until v out is within 250 mv of the regulated output voltage, or when v out drops out of regulation, and is lower than 300 mv below the regulated output voltage. a hysteresis of 50 mv is included in the function to minimize oscillations.
cs8101 http://onsemi.com 6 the reset output is an open collector npn transistor, controlled by a low voltage detection circuit. the circuit is functionally independent of the rest of the ic thereby guaranteeing that the reset signal is valid for v out as low as 1.0 v. figure 5. rc network for reset delay v out cs8101 5.0 v to p and system power reset r rst to p reset port c rst c out an external rc network on the lead (figure 5) provides a sufficiently long delay for most microprocessor based applications. rc values can be chosen using the following formula: r tot c rst ? t delay ln v t v out v rst v out where: r rst = reset delay resistor r in = p port impedance r tot = r rst in parallel with r in c rst = reset delay capacitor t delay = desired delay time v rst = v sat of reset lead (0.7 v @ turn ? on) v t = reset threshold. the circuit depicted in figure 6 lets the microprocessor control its power source, the cs8101 regulator. an i/o port on the p and the switch port are used to drive the base of q1. when q1 is driven into saturation, the voltage on the enable lead falls below its lower threshold. the regulator?s output is enabled. when the drive current is removed, the voltage on the enable lead rises, the output is switched off and the ic moves into sleep mode where it draws 50 a (max). by coupling these two controls with the enable lead, the system has added flexibility. once the system is running, the state of the switch is irrelevant as long as the i/o port continues to drive q1. the microprocessor can turn off its own power by withdrawing drive current, once the switch is open. this software control at the i/o port allows the microprocessor to finish key housekeeping functions before power is removed. the logic options are summarized in table 1. table 1. logic control of cs8101 output microprocessor i/o drive switch enable output on closed low on open low on off closed low on open high off the i/o port of the microprocessor typically provides 50 a to q1. in automotive applications the switch is connected to the ignition switch.
cs8101 http://onsemi.com 7 application notes v bat switch q1 500 k 0.1 f 500 k 100 k 100 k c rst c out r rst v cc reset i/o port p v out reset enable v in figure 6. microprocessor control of cs8101 using external switching transistor q1 cs8101 gnd the enable pin of the cs8101 can be tied to the battery voltage provided a series resistor is used as shown in figure 7. the maximum allowed voltage on the enable pin without the resistor is 10 v. direct voltages greater than 10 v applied to the pin without the series resistor may damage the device. the system designer should note the turn ? on threshold (typ 1.4 v) is on the enable pin. the threshold will be higher on the other side of r enable . v bat figure 7. using the enable pin with v bat 60 k enable r enable 0.64 v on/off control 10 k 50 k stability considerations the output or compensation capacitor helps determine three main characteristics of a linear regulator: start ? up delay, load transient response and loop stability. v in figure 8. test and application circuit showing output compensation c in * 0.1 f enable v out r rst c out ** 10 f reset cs8101 *c in required if regulator is located far from the power supply filter . *c out required for stability . capacitor must operate at minimum temperature expected. the capacitor value and type should be based on cost, availability, size and temperature constraints. a tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero esr can cause instability. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures ( ? 25 c to ? 40 c), both the value and esr of the capacitor will vary considerably. the capacitor manufacturers data sheet usually provides this information. the value for the output capacitor c out shown in figure 8 should work for most applications, however it is not necessarily the optimized solution.
cs8101 http://onsemi.com 8 to determine an acceptable value for c out for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. step 1: place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. a decade box connected in series with the capacitor will simulate the higher esr of an aluminum capacitor. leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. step 2: with the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. if no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. step 3: increase the esr of the capacitor from zero using the decade box and vary the load current until oscillations appear. record the values of load current and esr that cause the greatest oscillation. this represents the worst case load conditions for the regulator at low temperature. step 4: maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. this point represents the worst case input voltage conditions. step 5: if the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. a smaller capacitor will usually cost less and occupy less board space. if the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next lar ger standard capacitor value. step 6: test the load transient response by switching in various loads at several frequencies to simulate its real working environment. vary the esr to reduce ringing. step 7: raise the temperature to the highest specified operating temperature. vary the load current as instructed in step 5 to test for any oscillations. once the minimum capacitor value with the maximum esr is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. most good quality aluminum electrolytic capacitors have a tolerance of 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. the esr of the capacitor should be less than 50% of the maximum allowable esr found in step 3 above. calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 9) is: p d(max) v in(max) v out(min) i out(max)
v in(max) i q (1) where: v in(max) is the maximum input voltage, v out(min) is the minimum output voltage, i out(max) is the maximum output current for the application, and i q is the quiescent current the regulator consumes at i out(max) . once the value of p d(max) is known, the maximum permissible value of r ja can be calculated: r ja 150 c t a p d (2) the value of r ja can then be compared with those in the package section of the data sheet. those packages with r ja ?s less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. figure 9. single output regulator with key performance parameters labeled regulator ? control features i out i in i q v in v out heat sinks a heat sink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r ja . r ja r jc
r cs
r sa (3) where: r jc = the junction ? to ? case thermal resistance, r cs = the case ? to ? heatsink thermal resistance, and r sa = the heatsink ? to ? ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it is a function of package type. r cs and r sa are functions of the package type, heatsink and the interface between them. these values appear in heat sink data sheets of heat sink manufacturers.
cs8101 http://onsemi.com 9 device ordering information* device package shipping ? cs8101yd8g soic ? 8 (pb ? free) 98 units/rail cs8101ydr8g soic ? 8 (pb ? free) 2500/tape & reel cs8101ydwf20g so ? 20 wb (pb ? free) 38 units/tube cs8101ydwfr20g so ? 20 wb (pb ? free) 1000/tape & reel *contact your local sales representative for d 2 pak package option. ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. marking diagrams so ? 20 wb dwf suffix case 751d soic ? 8 d suffix case 751 20 1 cs8101 awlyywwg cs8101 = specific device code a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g = pb ? free package = pb ? free package cs810 alyw1 1 8
cs8101 http://onsemi.com 10 so ? 20 wb dwf suffix case 751d ? 05 issue g 20 1 11 10 b 20x h 10x c l 18x a1 a seating plane h x 45 e d m 0.25 m b m 0.25 s a s b t e t b a dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 12.65 12.95 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of b dimension at maximum material condition. package thermal data parameter soic ? 8 so ? 20 wb unit r jc typical 45 9.0 c/w r ja typical 165 55 c/w
cs8101 http://onsemi.com 11 soic ? 8 nb d suffix case 751 ? 07 issue aj 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. cs8101/d smart regulator is a trademark of semiconductor components industries, llc. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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